This application is based on Application No. 2001-320305, filed in Japan on Oct. 18, 2001, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a control circuit of a power converter (of the instantaneous current waveform control type), including switching elements which perform a plurality of switching operations in one cycle, for controlling the instantaneous magnitude of an output current of the power converter, and more specifically, it relates to a control circuit of a power converter such as a sinusoidal wave voltage output type inverter, including a motor driving inverter, a high power factor converter, an active filter and an LC filter.
2. Description of the Prior Art
FIG. 12 is a block diagram illustrating a known control circuit of a power converter, which is, for example, a control circuit of an inverter described in a section entitled xe2x80x9cCURRENT CONTROL TYPE PWM INVERTER CAPABLE OF HARMONIC CONTROL AND HIGH-SPEED CURRENT RESPONSExe2x80x9d (pages 9-16) in xe2x80x9cInstitute of Electrical Engineers proceedingsxe2x80x9d, Vol. 12B, No. 2 (1986), and modified into a control configuration associated with the present invention.
The control circuit shown in FIG. 12 is constructed as a current control loop for performing instantaneous current control.
In FIG. 12, the power converter in the form of a main circuit of a three-phase inverter 1 is comprised of a full bridge arrangement of three pairs of switching elements Tr1-Tr6, as shown in FIG. 13 for instance.
Current sensors 10U, 10V and 10W are connected with three output terminals, respectively, of the three-phase inverter 1 for detecting inverter currents IAU, IAV and IAW output from the three-phase inverter 1.
The current sensors 10U-10W constitute, together with a feedback control circuit (to be described later), a current loop for controlling the instantaneous magnitudes of the output currents IAU-IAW of the three-phase inverter 1.
A load 2 (for instance, three-phase motor) is connected with an output side of the three-phase inverter 1 and is provided with internal inductances 21U, 21V and 21W on which alternating current (AC) voltages VBU, VBV and VBW of U phase, V phase and W phase are imposed, respectively, and internal induction voltage sources 22U, 22V and 22W connected with the internal inductances 21U-21W, respectively.
The internal induction voltage sources 22U-22W generate counter electromotive forces VBOU, VBOV and VBOW for the internal inductances 21U-21W as three-phase induced voltages.
A direct current power supply 4 is connected with the three-phase inverter 1 for supplying a direct current (DC) source voltage VD to the three-phase inverter 1.
A three-phase sinusoidal wave current instruction generation circuit 801 generates current instruction values IAU*, IAV*, and IAW* of three-phase sinusoidal waves (to be supplied from the three-phase inverter 1) to the current loop formed on the output side of the three-phase inverter 1.
A current deviation vector detection circuit 802 calculates a voltage deviation vector associated with the internal induction voltage sources 22U-22W. A counterelectromotive force estimation circuit 803 estimates counterelectromotive forces VBOU-VBOW generated in the load 2.
A PWM pattern table circuit 804 determines the pattern of a PWM pulse for the three-phase inverter 1 in accordance with the output signals of the current deviation vector detection circuit 802 and the counterelectromotive force estimation circuit 803.
Adder-subtracters 851U, 851V and 851W are connected with the output side of the three-phase sinusoidal wave current instruction generation circuit 801.
The three-phase sinusoidal wave current instruction generation circuit 801 and the adder-subtracters 851U-851W together constitute a current instruction generation means, and calculate current deviations (current deviation vector) xcex94iU, xcex94iV and xcex94iW between the current instruction values IAU*-IAW* and the inverter currents (current feedback values) IAU-IAW, respectively.
Now, reference will be made to the operation of the known control circuit of the power converter as shown in FIG. 12 and FIG. 13 while referring to FIG. 14 through FIG. 17.
FIG. 14 and FIG. 15 are vector diagrams for explaining the operation of the known control circuit of the power converter.
In FIG. 14, there are shown eight kinds of voltage vectors V0-V7 which are output according to the states of the switching elements Tr1-Tr6 in the three-phase inverter 1, and six areas [P1]-[P6] delimited by the respective voltage vectors V0-V7.
In FIG. 15, there are shown an area [Q7] indicating that a current deviation vector xcex94I is in an allowable range, and outer peripheral areas [Q1]-[Q6] indicating that the current deviation vector xcex94I (e.g., xcex94Ia or xcex94Ib) is outside the allowable range.
FIG. 16 is an explanatory view which shows switching modes k0-k7 corresponding to the eight kinds of voltage vectors V0-V7, and switching states (ON/OFF) of the switching elements Tr1-Tr6 in the three-phase inverter 1 in the respective switching modes.
FIG. 17 is an explanatory view which shows a matrix condition for selecting switching modes k0-k7, wherein the horizontal direction of the matrix corresponds to the current deviation vector xcex94I and the vertical direction thereof corresponds to counterelectromotive force vector VB, respectively.
First of all, in FIG. 12, the adder-subtracters 851U-851W together constituting the current instruction generation means calculate current deviations xcex94iU-xcex94iW between current instruction values IAU*-IAW* generated from the three-phase sinusoidal wave current instruction generation circuit 801, and inverter currents IAU-IAW detected by the current sensors 10U-10W.
Then, the counterelectromotive force vector estimation circuit 803 estimates counterelectromotive forces VBU-VBW generated at input ends of the load 2 from the current deviations xcex94iU-xcex94iW, calculates the counterelectromotive force vector VB, and detects in which one of the areas [P1]-[P6] (see FIG. 14) the counterelectromotive force vector VB exists.
In addition, the current deviation vector detection circuit 802 calculates the current deviation vector xcex94I from the current deviations xcex94iU-xcex94iW, and detects in which one of the areas [Q1]-[Q7] (see FIG. 15) the current deviation vector xcex94I exists.
When a prescribed allowable range for the current deviation vector xcex94I determined according to the accuracy of the current control is set, the area [Q7] in FIG. 15 shows that the current deviation vector xcex94I is in the allowable range.
Moreover, the areas [Q1]-[Q6] outside the area [Q7] shows that the current deviation vector xcex94I (e.g., xcex94Ia or xcex94Ib) is outside the allowable range.
The PWM pattern table circuit 804 selects the switching modes k0-k7 from the areas [P1]-[P6] of the counterelectromotive force vector VB and the areas [Q1]-[Q7] of the current deviation vector xcex94I according to the two dimensional map of FIG. 17.
Moreover, the PWM pattern table circuit 804 determines the switching states of the switching elements Tr1-Tr6 (see FIG. 16) in the three-phase inverter 1 from the switching modes k0-k7.
In FIG. 17, in cases where the counterelectromotive force vector VB exists in the area [P1] for instance, the switching mode k1 is selected if the current deviation vector xcex94I exists in the area [Q1] or [Q5], and the switching mode k3 is selected if the current deviation vector xcex94I exists in the area [Q2] or [Q3].
In cases where the counterelectromotive force vector VB is in the area [P1], the switching mode k0 or k7 is selected if the current deviation vector xcex94I exists in the area [Q4] or [Q6], and the switching mode at that time is maintained as it is if the current deviation vector xcex94I exists in the area [Q7].
The respective switching elements Tr1-Tr6 in the three-phase inverter 1 are controlled to be turned on or off based on a switching instruction from the PWM pattern table circuit 804.
As a result, the inverter currents IAU-IAW are controlled to coincide with the current instruction values IAU*-IAW*.
Next, reference will be made to how the current deviation vector xcex94I changes in accordance with the above-mentioned control.
For example, let us consider that the counterelectromotive force vector VB is in the area [P1] in FIG. 14, and the current deviation vector xcex94I is indicated at xcex94Ia in the area [Q1] in FIG. 15.
In this state, the switching mode k1 is selected according to the map of FIG. 17, and the current deviation vector xcex94I moves in the direction of a difference vector VL1 between the counterelectromotive force vector VB and the voltage vector V1 (see FIG. 14).
At this time, the current deviation vector xcex94I or xcex94Ia, which exists in the area [Q1] outside the allowable range as indicated at an arrow in FIG. 15, comes into the area [Q7] in the allowable range.
However, in cases where the current deviation vector xcex94I is located at a position of xcex94Ib in FIG. 15, even if the switching mode k1 is selected, the current deviation vector xcex94I or xcex94Ib does not come into the area [Q7], but after having once moved into the area [Q3], the current deviation vector xcex94I moves, by the switching mode k3 being selected from the conditions of the area [P1] and the area [Q3], in the direction of VL3 (see FIG. 14), entering the area Q7 in the allowable range.
In this case, if the switching mode k3 has been selected immediately at the instant when the current deviation vector xcex94I is located in xcex94Ib (i.e., in [Q1]), the current deviation vector xcex94I moves along a broken line in FIG. 15 from the current deviation vector xcex94Ib, so that the current deviation vector xcex94I can be moved into the area [Q7] in the allowable range by changing the switching mode at one time. However, this is not considered at all in the above-mentioned known control circuit.
As described above, the known control circuit of the power converter has the following problem; that is, it is sometimes impossible to select an optimal switching mode at one time in which the current deviation vector xcex94I can enter the allowable range, and hence additional or extra switching is required, as a consequence of which losses of the switching elements Tr1-Tr6 are increased, reducing the efficiency of the three-phase inverter 1 (power converter).
The present invention is intended to obviate the problems as referred to above, and has for its object to provide a control circuit of a power converter which is capable of selecting an optimal switching mode for reducing the number of times of switchings.
Bearing the above object in mind, according to a first aspect of the present invention, there is provided a control circuit of a power converter which includes switching elements performing a plurality of times of switchings in one cycle, and which is connected with a three-phase voltage generator through reactors. The control circuit comprises: a current loop having a current sensor inserted in each of output terminals of the power converter for controlling an instantaneous magnitude of a corresponding output current of the power converter; current instruction generation means for providing current instruction values to the current loop; current deviation vector detection means for calculating a current deviation vector between the current instruction values and corresponding current feedback values from the current sensor; voltage detection means for calculating a voltage vector of the three-phase voltage generator; and PWM pattern selection means for selecting a PWM pattern for the power converter in accordance with the current deviation vector and the voltage vector. The PWM pattern selection means sets an allowable deviation range for the current deviation vector, and selects a switching mode for the power converter from among switching modes limited by values of the current deviation vector and the voltage vector when the current deviation vector deviates from the allowable deviation range, and outputs the PWM pattern. With this arrangement, it is possible to select an optimal switching mode for reducing the number of times of switchings.
In a preferred form of the first aspect of the present invention, the PWM pattern selection means calculates a passing-through time in which the current deviation vector passes through the allowable deviation range, and selects the switching mode in accordance with the passing-through time. Thus, it is possible to select an optimal switching mode for further reducing the number of times of switchings.
In another preferred form of the first aspect of the present invention, the PWM pattern selection means weights a specific switching mode determined by values of the voltage vector in accordance with the passing-through time, and preferentially outputs the specific switching mode to the power converter. Accordingly, even when the voltage vector is not selected based on the commercial power supply voltage vector, it is possible to select an optimal switching mode for reducing the number of times of switchings.
In a further preferred form of the first aspect of the present invention, when amounts of changes per unit time of the current instruction values are larger than a prescribed amount, the voltage detection means corrects the voltage vector by products of time derivatives of the current instruction values and inductance values of the reactors, respectively. Thus, even if the current instruction value changes, it is possible to select an optimal switching mode for reducing the number of times of switchings.
According to a second aspect of the present invention, there is provided a control circuit of a power converter which includes switching elements performing a plurality of times of switchings in one cycle, and which supplies three-phase AC voltages to a three-phase load through a filter circuit comprising reactors and capacitors. The control circuit comprises: a current loop having a current sensor inserted in each of output terminals of the power converter for controlling an instantaneous magnitude of a corresponding output current of the power converter; a voltage loop for controlling an instantaneous magnitude of each of output voltages of the power converter; voltage instruction generation means for providing voltage instruction values to the voltage loop; voltage deviation detection means for calculating voltage deviations between the voltage instruction values and corresponding voltage feedback values, respectively; voltage control means for outputting current instruction values for the current loop in accordance with the voltage deviations, respectively; current deviation vector detection means for calculating a current deviation vector between the current instruction values and corresponding current feedback values from the current sensor; and PWM pattern selection means for selecting a PWM pattern for the power converter in accordance with the current deviation vector and the voltage instruction values. The PWM pattern selection means sets an allowable deviation range for the current deviation vector, and selects a switching mode for the power converter from among switching modes limited by the current deviation vector and the voltage instruction values when the current deviation vector deviates from the allowable deviation range, and outputs the PWM pattern; and the voltage control means outputs the current instruction values so as to decrease the voltage deviation vector. With this arrangement, it is possible to select an optimal switching mode for reducing the number of times of switchings.
In a preferred form of the second aspect of the present invention, when amounts of changes per unit time of the current instruction values are larger than a prescribed amount, the voltage instruction generation means corrects the voltage instruction values by products of time derivatives of the current instruction values and inductance values of the reactors, respectively. Thus, even if the current instruction value changes, it is possible to select an optimal switching mode for reducing the number of times of switchings.
The above and other objects, features and advantages of the present invention will become more readily apparent to those skilled in the art from the following detailed description of preferred embodiments of the present invention taken in conjunction with the accompanying drawings.